UC17131/2/3
UC27131/2/3
UC37131/2/3
DESCRIPTION OF OPERATION
Reference
current of approximately 4µA. If the power stays off lon-
ger than this time, then a power up delay will be initial-
ized once power is resumed. This delay is the time it
The UC37131/2/3 family of devices features a 6V
bandgap reference that is used to bias on-chip logic. Al-
though the 6V reference is not trimmed, this bandgap ref-
erence provides less than 200ppm/°C. It is also used to
generate the on-chip 3V input comparator threshold and
is needed for the programmable hysteresis. The on-chip
reference has 8mA maximum current sourcing capacity
that is designed to power up external circuitry.
takes for CDEL to charge from 0V to V
of 4.9V.
FAULT_H
The overcurrent fault normal operation consists of the
chip staying off until CDEL fully recharges to V of
FAULT_H
4.9V. This is t . Once CDEL reaches 4.9V, the driver
R(OFF)
will turn back on. If the overcurrent fault is still present,
the chip will operate in a very low duty cycle (approxi-
mately 0.7%) based on the discharge (driver on) and
charge time (driver off) of the CDEL capacitor. This
overcurrent timing makes the chip act "smart" by allowing
very high currents needed to drive large capacitive loads
without setting off an overcurrent fault.
Input Comparator
The input comparator is a high gain comparator with hys-
teresis that fully switches with either a small signal
(30mV, minimum for 1% hysteresis) or a logic signal (0 to
6V max). Only a 5mV overdrive of the 3V threshold is
needed to switch the driver.
The overcurrent and current limit thresholds are pro-
grammed with the resistor R
from CSH to VCC (high
CSH
The hysteresis is set to 30% on the UC37131 and
UC37133. (This is 30% of 3V equating to 0.9V of hyster-
esis.) On the UC37132 it is programmable from 1% to
30%.
side) or R
a 150mV (I
from CSL to GND (low side). For example,
CSL
• R ) threshold will set the high side
CSH
LOAD
overcurrent fault threshold. An overall short circuit protec-
tion threshold is set at 300mV. Therefore, the recom-
mended R
of 0.5Ω will result in the 600mA short
Fault Logic
CSH
circuit. By changing the R
mally set the overcurrent and short circuit current limits.
value the user can opti-
CSH
The output of the comparator is logic ANDed with the
output of the fault logic. If a fault, either a power interrupt
or an overcurrent condition, persists longer than it takes
Output Driver
for the CDEL to discharge from its V
level of
CDEL_MAX
Once the turn-on signal is gated through from the input
comparator, the output transistor is turned on. The output
drive transistor is a composite PNP, NPN structure. This
is a specially designed structure that keeps all the drive
current needed for the load to be sourced through the LS
pin. This keeps the overall power dissipation to less than
4mA independent of the load.
5.8V to its V
of 1.3V, the fault protection block will
FAULT_L
output a logic 0 to the NAND gate and turn off the output
driver. If the fault goes away prior to CDEL being dis-
charged to 1.3V, the chip will resume normal operation
without going through a turn-on delay.
The power interrupt normal operation consists of the chip
turning the driver immediately back on if the interrupt
goes away prior to CDEL reaching its lower threshold as
described above. The CDEL capacitor is chosen based
upon the maximum power interrupt time (t ) allowed
without the output experiencing a turn-on delay. This in-
The output driver also has a 72V zener diode wired be-
tween its base and collector. This allows the output to
swing and clamp to 72V above ground when discharging
an inductive load in a low side application. The inductive
zener clamp can discharge the 250mA to 400mA full
load current. This consequently allows the LS pin to
safely swing above VCC. Similarly, the 72V zener diode
will allow the HS pin to safely swing and clamp 72V be-
low LS/VCC when discharging an inductive load in a high
side application. This 72V zener diode simplifies the user
application by eliminating the need for external clamp di-
odes.
INT
terrupt time must be less than t
where t
is
D(OFF)
D(OFF)
equal to the time it takes the CDEL capacitor to dis-
charge from V (5.8V) to V (1.3V) with a
CDEL_MAX
FAULT_L
discharge current of approximately 94µA. If the power
stays off only as long as t , the minimum power up
D(OFF)
delay will be equal to the time it takes to charge CDEL
from V (1.3V) to V (4.9V) with a charge
FAULT_L
FAULT_H
6
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