TVP5160
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SLES135E–FEBRUARY 2005–REVISED APRIL 2011
Table 3-129. Interrupt Raw Status 1
Subaddress F1h
Read only
7
6
5
4
3
2
1
0
Reserved
FIFO full
FIFO full:
0 = FIFO not full
1 = FIFO was full during write to FIFO
The masked or unmasked status is set in the interrupt mask 1 register at subaddress F5h.
The FIFO full error flag is set when the current line of VBI data can not enter the FIFO. For example, if the FIFO has only 10 bytes left and
teletext is the current VBI line, the FIFO full error flag is set, but no data will be written because the entire teletext line will not fit. However, if
the next VBI line is closed caption requiring only 2 bytes of data plus the header, then this will go into the FIFO even if the full error flag is
set.
Table 3-130. Interrupt Status 0
Subaddress F2h
Read only
7
6
5
4
3
2
1
0
FIFO THRS
TTX
WSS/CGMS
VPS/Gemstar
VITC
CC F2
CC F1
Line
FIFO THRS: FIFO threshold passed, masked
0 = Not passed
1 = Passed
TTX: Teletext data available masked
0 = Not available
1 = Available
WSS/CGMS: WSS/CGMS data available masked
0 = Not available
1 = Available
VPS/Gemstar: VPS/Gemstar data available masked
0 = Not available
1 = Available
VITC: VITC data available masked
0 = Not available
1 = Available
CC F2: CC field 2 data available masked
0 = Not available
1 = Available
CC F1: CC field 1 data available masked
0 = Not available
1 = Available
Line: Line number interrupt masked
0 = Not available
1 = Available
The interrupt status 0 and 1 registers represent the interrupt status after applying mask bits. Therefore, the status bits are the result of a
logical AND between the raw status and mask bits. The external interrupt pin is derived from this register as an OR function of all
nonmasked interrupts in this register.
Reading data from the corresponding register does not clear the status flags automatically. These flags are reset using the corresponding
bits in interrupt clear 0 and 1 registers.
Copyright © 2005–2011, Texas Instruments Incorporated
Internal Control Registers
85
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