TVP5160
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SLES135E–FEBRUARY 2005–REVISED APRIL 2011
Table 3-122. VDP Full Field Mode
Subaddress DAh
Default
FFh
7
6
5
4
3
2
1
0
Full field mode [7:0]
Full field mode [7:0]: This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual line settings
take priority over the full field register. This allows each VBI line to be programmed independently but have the remaining lines in full field
mode. The full field mode register has the same bits definition as line mode registers. (default FFh)
Global line mode will have priority over the full field mode.
Table 3-123. Interlaced/Progressive Status
Subaddress DBh
Read only
7
6
5
4
3
2
1
0
I/P
Interlaced/progressive detection status:
0 = SD interlaced signal detected
1 = ED/HD signal detected
Table 3-124. VBUS Data Access with No VBUS Address Increment
Subaddress E0h
Default 00h
7
6
5
4
3
2
1
0
VBUS data [7:0]
VBUS data [7:0]: VBUS data register for VBUS single byte read/write transaction.
Table 3-125. VBUS Data Access with VBUS Address Increment
Subaddress E1h
Default 00h
7
6
5
4
3
2
1
0
VBUS data [7:0]
VBUS data [7:0]: VBUS data register for VBUS multi-byte read/write transaction. VBUS address is auto-incremented after each data byte
read/write.
Table 3-126. VDP FIFO Read Data
Subaddress E2h
Read only
7
6
5
4
3
2
1
0
FIFO Read Data [7:0]
FIFO Read Data [7:0]: This register is provided to access VBI FIFO data through the I2C interface. All forms of teletext data come directly
from the FIFO, while all other forms of VBI data can be programmed to come from registers or from the FIFO. If the host port reads data
from the FIFO, then bit 0 (host access enable) in the VDP FIFO output control register at subaddress C0h must be set to 1b.
Copyright © 2005–2011, Texas Instruments Incorporated
Internal Control Registers
83
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