TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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Table 3-127. VBUS Address
Subaddress
Default
E8h
00h
E9h
00h
EAh
00h
Subaddress
E8h
7
6
5
4
3
2
1
0
VBUS address [7:0]
VBUS address [15:8]
VBUS address [23:16]
E9h
EAh
VBUS address [23:0]: VBUS is a 24-bit wide internal bus. The user must program the 24-bit
address of the internal register to be accessed via host port indirect access mode.
Table 3-128. Interrupt Raw Status 0
Subaddress F0h
Read only
7
6
5
4
3
2
1
0
FIFO THRS
TTX
WSS/CGMS
VPS/Gemstar
VITC
CC F2
CC F1
Line
FIFO THRS: FIFO threshold passed, unmasked
0 = Not passed
1 = Passed
TTX: Teletext data available unmasked
0 = Not available
1 = Available
WSS/CGMS: WSS/CGMS data available unmasked
0 = Not available
1 = Available
VPS/Gemstar: VPS/Gemstar data available unmasked
0 = Not available
1 = Available
VITC: VITC data available unmasked
0 = Not available
1 = Available
CC F2: CC field 2 data available unmasked
0 = Not available
1 = Available
CC F1: CC field 1 data available unmasked
0 = Not available
1 = Available
Line: Line number interrupt unmasked
0 = Not available
1 = Available
The host interrupt raw status 0 and 1 registers represent the interrupt status without applying mask bits.
84
Internal Control Registers
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