TSC2007
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SBAS405–MARCH 2007
TIMING REQUIREMENTS: I2C High-Speed Mode (SCL = 3.4MHz)
All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS
SCL clock frequency
TEST CONDITIONS
MIN
0
TYP MAX UNIT
fSCL
3.4 MHz
Hold time (repeated) START condition
Low period of SCL clock
tHD, STA
tLOW
tHIGH
tSU, STA
tHD, DAT
tSU, DAT
tR
160
160
60
ns
ns
ns
ns
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
160
0
70
ns
ns
ns
Data setup time
10
Rise time for SCL clock signal (receiving)
Rise time for SDA clock signal (receiving)
Fall time for SCL clock signal (receiving)
Fall time for SDA clock signal (receiving)
Fall time for both SDA and SCL clock signals (transmitting)
Setup time for STOP condition
Cb = total bus capacitance
Cb = total bus capacitance
Cb = total bus capacitance
Cb = total bus capacitance
Cb = total bus capacitance
10
40
80
40
80
80
tR
10
tF
10
ns
tF
10
tOF
10
ns
ns
tSU, STO
Cb
160
Capacitive load for each bus line
Cb = total capacitance of one bus line in pF
40 SCL + 127 CCLK, VDD = 1.8V
49 SCL + 148 CCLK, VDD = 1.8V
VDD = 1.8V
100
pF
8 bits
46.5
95.3
µs
Cycle time
12 bits
µs
8 bits
21.52
10.49
150.65
73.46
kSPS
kSPS
kHz
kHz
Effective throughput
12 bits
VDD = 1.8V
8 bits
Equivalent rate = effective throughput × 7
12 bits
VDD = 1.8V
VDD = 1.8V
8
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