TSC2007
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SBAS405–MARCH 2007
TIMING REQUIREMENTS: I2C Fast Mode (SCL = 400kHz)
All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.
2-WIRE FAST MODE PARAMETERS
SCL clock frequency
TEST CONDITIONS
MIN
TYP MAX UNIT
fSCL
0
400 kHz
Bus free time between a STOP and START condition
Hold time (repeated) START condition
Low period of SCL clock
tBUF
1.3
µs
µs
µs
µs
µs
tHD, STA
tLOW
0.6
1.3
High period of the SCL clock
tHIGH
tSU, STA
tHD, DAT
tSU, DAT
tR
0.6
Setup time for a repeated START condition
Data hold time
0.6
0
0.9
µs
ns
Data setup time
100
Rise time for both SDA and SCL clock signals (receiving)
Fall time for both SDA and SCL clock signals (receiving)
Cb = total bus capacitance
20+0.1×Cb
20+0.1×Cb
20+0.1×Cb
0.6
300
300
250
ns
tF
Cb = total bus capacitance
Cb = total bus capacitance
ns
Fall time for both SDA and SCL clock signals (transmitting) tOF
ns
Setup time for STOP condition
Capacitive load for each bus line
tSU, STO
Cb
µs
Cb = total capacitance of one bus line in pF
40 SCL + 127 CCLK, VDD = 1.8V
49 SCL + 148 CCLK, VDD = 1.8V
VDD = 1.8V
400
pF
8 bits
134.7
203.4
7.42
µs
Cycle time
12 bits
8 bits
µs
kSPS
kSPS
kHz
kHz
Effective throughput
12 bits
8 bits
VDD = 1.8V
4.92
VDD = 1.8V
51.97
34.42
Equivalent rate = effective throughput × 7
12 bits
VDD = 1.8V
TIMING REQUIREMENTS: I2C High-Speed Mode (SCL = 1.7MHz)
All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS
SCL clock frequency
TEST CONDITIONS
MIN
0
TYP MAX UNIT
fSCL
1.7 MHz
Hold time (repeated) START condition
Low period of SCL clock
tHD, STA
tLOW
tHIGH
tSU, STA
tHD, DAT
tSU, DAT
tR
160
320
120
160
0
ns
ns
ns
ns
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
150
ns
ns
Data setup time
10
Rise time for SCL clock signal (receiving)
Rise time for SDA clock signal (receiving)
Fall time for SCL clock signal (receiving)
Fall time for SDA clock signal (receiving)
Fall time for both SDA and SCL clock signals (transmitting)
Setup time for STOP condition
Cb = total bus capacitance
Cb = total bus capacitance
Cb = total bus capacitance
Cb = total bus capacitance
Cb = total bus capacitance
20
80
160
80
ns
tR
20
ns
tF
20
ns
tF
20
160
80
ns
tOF
10
ns
tSU, STO
Cb
160
ns
Capacitive load for each bus line
Cb = total capacitance of one bus line in pF
40 SCL + 127 CCLK, VDD = 1.8V
49 SCL + 148 CCLK, VDD = 1.8V
VDD = 1.8V
400
pF
8 bits
58.2
109.7
17.17
9.12
µs
Cycle time
12 bits
µs
8 bits
kSPS
kSPS
kHz
kHz
Effective throughput
12 bits
VDD = 1.8V
8 bits
Equivalent rate = effective throughput × 7
12 bits
VDD = 1.8V
120.22
63.81
VDD = 1.8V
7
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