TSC2007
www.ti.com
SBAS405–MARCH 2007
PIN CONFIGURATION
PW PACKAGE
TSSOP-16
(TOP VIEW)
YZG PACKAGE
WCSP-12
(TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE)
X-
A1
X+
Y+
A0
Y-
AUX
NC
VDD/REF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
3
2
1
X+
Y+
VDD/REF
GND
SCL
A0
A1
X-
TSC2007
SDA
AUX
A
PENIRQ
B
SCL
SDA
PENIRQ
NC
Y-
GND
NC
NC
C
D
Columns
(FRONT VIEW)
PIN ASSIGNMENTS
PIN NO.
TSSOP WCSP
PIN
NAME
VDD/REF
X+
I/O
A/D DESCRIPTION
Supply voltage and external reference input
X+ channel input
1
2
A2
A3
B3
C3
D3
D2
—
I
I
I
I
A
A
A
A
3
Y+
Y+ channel input
X– channel input
Y– channel input
Ground
4
X–
5
Y–
6
GND
NC
7
No connection
No connection
No connection
8
—
NC
9
—
NC
10
11
B1
C1
PENIRQ
SDA
O
D
D
Data available interrupt output. A delayed (process delay) pen touch detect. Pin polarity with active low.
Serial data I/O
I/O
Serial clock. This pin is normally an input, but acts as an output when the device stretches the clock to
delay a bus transfer.
12
D1
SCL
I/O
D
13
14
15
16
C2
B2
—
A1
A0
I
I
D
D
Address input bit 1
Address input bit 0
No connection
NC
A1
AUX
I
A
Auxiliary channel input
5
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