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TPS7H5008MPWTSEP 参数 Datasheet PDF下载

TPS7H5008MPWTSEP图片预览
型号: TPS7H5008MPWTSEP
PDF下载: 下载PDF文件 查看货源
内容描述: [TPS7H500x-SEP Radiation-Tolerant 2-MHz Current Mode PWM Controllers in Space Enhanced Plastic]
分类和应用:
文件页数/大小: 71 页 / 4323 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TPS7H5005-SEP, TPS7H5006-SEP, TPS7H5007-SEP, TPS7H5008-SEP  
www.ti.com  
SLVSGG1 – FEBRUARY 2022  
7.7 Electrical Characteristics: TPS7H5006-SEP  
TJ = –55°C to 125°C, VIN = 4 V to 14 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
MINIMUM ON-TIME AND DEAD TIME  
tMIN  
Minimum on-time  
LEB = 10 kΩ, 5 V ≤ VIN ≤ 14 V  
85  
11  
ns  
PS = floating, 5 V ≤ VIN ≤ 14 V, 90%  
of OUTx falling to 10% of SRx rising,  
OUTx and SRx floating  
5
43  
85  
5
8
50  
PS = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V, 90%  
TDPS  
Primary off to secondary on dead time of OUTx falling to 10% of SRx rising,  
OUTx and SRx floating  
55  
110  
11  
ns  
PS = 107 kΩ, 5 V ≤ VIN ≤ 14 V, 90%  
of OUTx falling to 10% of SRx rising,  
OUTx and SRx floating  
100  
8
SP = floating, 5 V ≤ VIN ≤ 14 V, 90%  
of SRx falling to 10% of OUTx rising,  
OUTx and SRx floating  
SP = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V, 90% of  
Secondary off to primary on dead time SRx falling to 10% of OUTx rising edge,  
OUTx and SRx floating  
TDSP  
43  
85  
50  
55  
ns  
SP = 107 kΩ, 5 V ≤ VIN ≤ 14 V, 90%  
of SRx falling to 10% of OUTx rising,  
OUTx and SRx floating  
100  
110  
LEADING EDGE BLANK TIME AND DUTY CYCLE  
LEB = 10 kΩ, 5 V ≤ VIN ≤ 14 V  
LEB = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V  
LEB = 110 kΩ, 5 V ≤ VIN ≤ 14 V  
DCL = floating, clock duty cycle = 50%  
DCL = VLDO  
12  
45  
85  
70  
15  
50  
19  
55  
TLEB  
Leading edge blank time  
Maximum duty cycle  
ns  
%
100  
75  
110  
80  
DMAX  
100  
7.8 Electrical Characteristics: TPS7H5007-SEP  
TJ = –55°C to 125°C, VIN = 4 V to 14 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
MINIMUM ON-TIME AND DEAD TIME  
tMIN  
Minimum on-time  
5 V ≤ VIN ≤ 14 V  
115  
60  
ns  
ns  
5 V ≤ VIN ≤ 14 V, 90% of OUTx falling  
TDPS  
Primary off to secondary on dead time to 10% of SRx rising, OUTx and SRx  
floating  
40  
40  
50  
50  
5 V ≤ VIN ≤ 14 V, 90% of SRx falling  
Secondary off to primary on dead time to 10% of OUTx rising edge, OUTx and  
SRx floating  
TDSP  
60  
ns  
LEADING EDGE BLANK TIME AND DUTY CYCLE  
TLEB  
Leading edge blank time  
5 V ≤ VIN ≤ 14 V  
45  
70  
50  
75  
55  
80  
ns  
%
DCL = floating, clock duty cycle = 50%  
DCL = VLDO  
DMAX  
Maximum duty cycle  
100  
Copyright © 2022 Texas Instruments Incorporated  
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Product Folder Links: TPS7H5005-SEP TPS7H5006-SEP TPS7H5007-SEP TPS7H5008-SEP  
 
 
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