TPS54610
SLVS398D − JUNE 2001 − REVISED JULY 2003
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
−40°C to 85°C
OUTPUT VOLTAGE
Adjustable down to 0.9 V
PACKAGE
Plastic HTSSOP (PWP)(1)
PART NUMBER
TPS54610PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54610PWPR). See the application section of
the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS54610
VIN, SS/ENA, SYNC
RT
Input voltage range, VI
VSENSE
BOOT
VBIAS, COMP, PWRGD
Output voltage range, VO
Source current, IO
PH
PH
COMP, VBIAS
PH
Sink current, IS
Voltage differential
Operating virtual junction temperature range, TJ
Storage temperature, Tstg
COMP
SS/ENA, PWRGD
AGND to PGND
−0.3 V to 7 V
−0.3 V to 6 V
−0.3 V to 4V
−0.3 V to 17 V
−0.3 V to 7 V
−0.6 V to 10 V
Internally Limited
6
12
6
10
±0.3
−40 to 125
−65 to 150
mA
V
°C
°C
mA
A
V
V
UNIT
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage, VI
Operating junction temperature, TJ
3
−40
NOM
MAX
6
125
UNIT
V
°C
DISSIPATION RATINGS
(1)(2)
PACKAGE
28 Pin PWP with solder
28 Pin PWP without solder
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
18.2
°C/W
40.5
°C/W
TA = 25°C
POWER RATING
5.49 W(3)
2.48 W
TA = 70°C
POWER RATING
3.02 W
1.36 W
TA = 85°C
POWER RATING
2.20 W
0.99 W
(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2) Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
(3) Maximum power dissipation may be limited by over current protection.
2
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