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TPS54386PWPR 参数 Datasheet PDF下载

TPS54386PWPR图片预览
型号: TPS54386PWPR
PDF下载: 下载PDF文件 查看货源
内容描述: 3 -A双路非同步转换器,集成高边MOSFET [3-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE MOSFET]
分类和应用: 转换器稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件页数/大小: 52 页 / 1214 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TPS54383, TPS54386  
www.ti.com  
SLUS774BAUGUST 2007REVISED OCTOBER 2007  
DEVICE INFORMATION  
PIN CONNECTIONS  
HTSSOP (PWP)  
(Top View)  
PVDD1  
BOOT1  
SW1  
GND  
EN1  
1
2
3
4
5
6
7
14 PVDD2  
13 BOOT2  
12 SW2  
11 BP  
Thermal Pad  
(bottom side)  
10 SEQ  
EN2  
9
8
ILIM2  
FB2  
FB1  
TERMINAL FUNCTIONS  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
NO.  
Input supply to the high side gate driver for Output 1. Connect a 22-nF to 82-nF capacitor from this pin  
to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is  
turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small  
resistor (1 to 3 ) may be placed in series with the bootstrap capacitor.  
BOOT1  
2
I
Input supply to the high side gate driver for Output 2. Connect a 22-nF to 82-nF capacitor from this pin  
to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is  
turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small  
resistor (1 to 3 ) may be placed in series with the bootstrap capacitor.  
BOOT2  
BP  
13  
11  
5
I
-
I
Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low ESR (4.7-µF  
to 10-µF X7R or X5R) ceramic capacitor.  
Active low enable input for Output 1. If the voltage on this pin is greater than 1.55 V, Output 1 is  
disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 1 and allows soft start of  
Output 1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to  
GND for "always ON" operation.  
EN1  
Active low enable input for Output 2. If the voltage on this pin is greater than 1.55 V, Output 2 is  
disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 2 and allows soft start of  
Output 2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to  
GND for "always ON" operation.  
EN2  
FB1  
6
7
I
I
Voltage feedback pin for Output 1. The internal transconductance error amplifier adjusts the PWM for  
Output 1 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from  
Output 1 to ground, with the center connection tied to this pin, determines the value of the regulated  
output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback  
Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information.  
Voltage feedback pin for Output 2. The internal transconductance error amplifier adjusts the PWM for  
Output 2 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from  
Output 2 to ground, with the center connection tied to this pin, determines the value of the regulated  
Output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback  
Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information.  
FB2  
8
4
9
I
-
I
GND  
ILIM2  
Ground pin for the device. Connect directly to Thermal Pad.  
Current limit adjust pin for Output 2 only. This function is intended to allow a user with asymmetrical  
load currents (Output 1 load current much greater than Output 2 load current) to optimize component  
scaling of the lower current output while maintaining proper component derating in a overcurrent fault  
condition. The discrete levels are available as shown in Table 2, Current Limit Threshold Adjustment for  
Output 2. Note: An internal 2-resistor divider (150-keach) connects BP to ILIM2 and to GND.  
Power input to the Output 1 high side MOSFET only. This pin should be locally bypassed to GND with a  
low ESR ceramic capacitor of 10-µF or greater.  
PVDD1  
PVDD2  
1
I
I
The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2  
pins and provides power to the Output 2 high-side MOSFET. This pin should be locally bypassed to  
GND with a low ESR ceramic capacitor of 10-µF or greater. The UVLO function monitors PVDD2 and  
enables the device when PVDD2 is greater than 4.1 V.  
14  
Copyright © 2007, Texas Instruments Incorporated  
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9
Product Folder Link(s): TPS54383 TPS54386