TPS51640A, TPS59640, TPS59641
SLUSAQ2 –JANUARY 2012
www.ti.com
Grounding Recommendations
These devices have separate analog and power grounds, and a thermal pad. The normal procedure for
connecting these is:
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The thermal pad is the analog ground.
DO NOT connect the thermal pad to Pin 42 directly as Pin 42 is the PGND which is the Gate driver
Ground.
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Pin 42 (PGND) must be connected directly to the gate driver decoupling capacitor ground terminal.
Tie the thermal pad (analog ground pin) to a ground island with at least 4 small vias or one large via.
All the analog components can connect to this analog ground island.
The analog ground can be connected to any quiet spot on the system ground. A quiet area is defined as a
area where no power supply switching currents are likely to flow. This applies to both the VCORE regulator and
other regulators. Use a single point connection from analog ground to the system ground
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Make sure the low-side FET source connection and the decoupling capacitors have plenty of vias.
Decoupling Recommendations
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Decouple V5IN to PGND with at least a 2.2 µF ceramic capacitor.
Decouple V5 and V3R3 with 1 µF to AGND with leads as short as possible,
VREF to AGND with 0.33 µF, with short leads also
Conductor Widths
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Follow Intel guidelines with respect to the voltage feedback and logic interface connection requirements.
Maximize the widths of power, ground and drive signal connections.
For conductors in the power path, be sure there is adequate trace width for the amount of current flowing
through the traces.
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Make sure there are sufficient vias for connections between layers. A good guideline is to use a minimum of 1
via per ampere of current.
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