TPS51117
SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
DETAILED DESCRIPTION (continued)
PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL
The TPS51117 employs an adaptive on-time control scheme and does not have a dedicated oscillator on board.
However, the device emulates a constant frequency by feed-forwarding the input and output voltages into the
on-time one-shot timer. The ON time is controlled inverse proportional to the input voltage, and proportional to
the output voltage, so that the duty ratio is kept as VOUT/VIN technically with the same cycle time. Equation 3
shows a simplified calculation of the on time.
(2ń3)V
) 100 mV
OUT
V
T
+ 19 10*12 R
) 50 ns
ǒ
Ǔ
ON
TON
IN
(3)
Here, RTON is the external resistor connected from TON pin to the LL node. In the equation, 19 pF represents the
internal timing capacitor with some typical parasitic capacitance at the TON pin. Also, 50 nsec is the turn-off
delay time contributed by the internal circuit and that of the high-side MOSFET. Although this equation provides a
good approximation to start with, the accuracy depends on each design and selection of the high-side MOSFET.
Figure 1 shows the relationship of RTON to the switching frequency.
700
V
V
= 15 V,
IN
600
= 2.5 V,
OUT
PWM
500
400
300
200
100
0
100
200
300
400
- kW
500
600
R
TON
Figure 1. Switching Frequency vs RTON
The TPS51117 does not have a pin connected to VIN, but the input voltage information comes from the switch
node (LL node) during the ON state. An advantage of LL monitoring is that the loss in the high-side NFET is now
a part of the on-time calculation, thereby making the frequency more stable with load.
Another consideration about frequency is jitter. Jitter may be caused by many reasons, but the constant on-time
D-CAP mode scheme has some amount of inherent jitter. Since the output voltage ripple height is in the range of
a couple of tens of milli-volts. A milli-volt order of noise on the feedback signal can affect the frequency by a few
to ten percent. This is normal operation and has little harm to the power supply performance.
LOW-SIDE DRIVER
The low-side driver is designed to drive high-current, low RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which is 5 Ω for V5DRV to DRVL and 1.5 Ω for DRVL to PGND. A dead
time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on,
and low-side MOSFET off to high-side MOSFET on. A 5-V bias voltage is delivered from V5DRV supply. The
average drive current is calculated by the FET gate charge at Vgs = 5 V times the switching frequency. The
instantaneous drive current is supplied by an input capacitor connected between V5DRV and GND.
8
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