TPS51117
SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
DETAILED DESCRIPTION (continued)
NEGATIVE OVERCURRENT LIMIT (PWM-ONLY MODE)
The TPS51117 also supports cycle-by-cycle negative overcurrent limiting in PWM-only mode. The overcurrent
limit is set to be negative but is the same absolute value as the positive overcurrent limit. If output voltage
continues to rise, the bottom MOSFET stays on, thus inductor current is reduced and reverses direction after it
reaches zero. When there is too much negative current in the inductor, the bottom MOSFET is turned off and the
current flows to VIN through the body diode of the top MOSFET. Because this protection reduces current to
discharge the output capacitor, output voltage tends to rise, eventually hitting the overvoltage protection
threshold and shutdown. In order to prevent false OVP from triggering, the bottom MOSFET is turned on again
400 ns after it is turned off. If the device hits the negative overcurrent threshold again before output voltage is
discharged to the target level, the bottom MOSFET is turned off and the process repeats, which is called NOCL
Buzz. It ensures maximum allowable discharge capability when output voltage continues to rise. On the other
hand, if the output voltage is discharged to the target level before the NOCL threshold is reached, the bottom
MOSFET is turned off, the top MOSFET is then turned on, and the device resumes normal operation.
OVERVOLTAGE PROTECTION
The TPS51117 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage condition.
When the feedback voltage becomes higher than 115% of the target value, the top MOSFET is turned off and
the bottom MOSFET is turned on immediately. The output is also discharged by the internal 20-Ω transistor.
Also, the TPS51117 monitors VOUT terminal voltage directly and if it becomes greater than 5.75 V, it turns off
the top MOSFET driver.
UNDERVOLTAGE PROTECTION
When the feedback voltage becomes lower than 70% of the target value, the UVP comparator output goes high
and an internal UVP delay counter begins counting. After 32 μs, the TPS51117 latches off the high-side and
low-side MOSFETs and discharges the output with the internal 20-Ω transistor. This function is enabled after 2
ms from when EN_PSV is brought high, i.e., UVP is disabled during start up.
START UP SEQUENCE
Referring to Figure 2 which illustrates the timing sequence, to guarantee the proper startup the TPS51117,
always ensure that VEN_PSV is less or equal to that of VV5FILT prior to VV5FILT reaching VUVLO
.
5V UVLO
V5DRV
V5FILT
EN_PSV
VOUT
PGOOD
UDG-09142
t – Time
Figure 2. Startup Timing Sequence
10
Submit Documentation Feedback
Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS51117
TI [ TEXAS INSTRUMENTS ]
