TPS51117
www.ti.com...................................................................................................................................... SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
High-side NFET gate driver output. Source 5 Ω, sink 1.5 Ω LL-node referenced driver. Drive voltage
corresponds to VBST to LL voltage.
DRVH
13
O
O
I
Rectifying (low-side) NFET gate driver output. Source 5 Ω, sink 1.5 Ω PGND referenced driver. Drive voltage
is V5DRV voltage.
DRVL
9
1
Enable/power save pin. Connect to ground to disable SMPS. Connect to 3.3 V or 5 V to turn on SMPS and
activate skip mode. Float to turn on SMPS but disable skip mode (forced continuous conduction mode).
EN_PSV
GND
LL
7
I
Signal ground pin.
12
I/O
High-side NFET gate driver return. Also serves as anode of overcurrent comparator.
Ground return for rectifying NFET gate driver. Also cathode of overcurrent protection and source node of the
output discharge switch.
PGND
8
I/O
Power-good window comparator, open-drain, output. Pull up to 5-V rail with a pull-up resistor. Current
capability is 7.5 mA.
PGOOD
TON
6
2
O
I
On-time / frequency adjustment pin. Connect to LL with 100-kΩ to 600-kΩ resistor.
Overcurrent trip point set input. Connect resistor from this pin to signal ground to set threshold for both
overcurrent and negative overcurrent limit.
TRIP
11
I
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to LL-node. An
internal PN diode is connected between V5DRV to this pin. Designer can add external schottky diode if
forward drop is critical to drive the power NFET.
VBST
14
I
VFB
5
3
I
I
SMPS voltage feedback input. Connect the resistor divider here for adjustable output.
Connect to SMPS output. This terminal serves two functions: output voltage monitor for on-time adjustment,
and input for the output discharge switch.
VOUT
5-V Power supply input for FET gate drivers. Internally connected to VBST by a PN diode. Connect 1 μF or
more between this pin and PGND to support instantaneous current for gate drivers.
V5DRV
V5FILT
10
4
I
I
5-V Power supply input for all the control circuitry except gate drivers. Supply 5-V ramp rate should be 17
mV/μs or less and Tj < 85°C to secure safe start-up of the internal reference circuit. Apply RC filter consists of
300 Ω + 1 μF or 100 Ω + 4.7 μF at the pin input.
QFN (RGY) PACKAGE
(BOTTOM VIEW)
TSSOP (PW) PACKAGE
(TOP VIEW)
14
13
12
11
10
9
1
2
3
4
5
6
7
EN_PSV
TON
VBST
DRVH
LL
14
1
13
12
11
10
9
2
3
4
5
6
TON
VOUT
V5FILT
VFB
DRVH
LL
VOUT
V5FILT
VFB
TRIP
TRIP
V5DRV
DRVL
PGND
V5DRV
DRVL
PGOOD
GND
PGOOD
8
8
7
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