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TPS23750PWPR 参数 Datasheet PDF下载

TPS23750PWPR图片预览
型号: TPS23750PWPR
PDF下载: 下载PDF文件 查看货源
内容描述: 结合100 -V型IEEE 802.3af PD和DC / DC控制器 [INTEGRATED 100-V IEEE 802.3af PD AND DC/DC CONTROLLER]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管PC
文件页数/大小: 38 页 / 2852 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TPS23750  
TPS23770  
www.ti.com  
SLVS590AJULY 2005REVISED AUGUST 2005  
RECOMMENDED OPERATING CONDITIONS(1)(2)  
All voltage values are with respect to VSS unless otherwise noted.  
MIN  
0
NOM  
MAX UNIT  
VDD  
Input voltage range(3)  
Input voltage range  
COM, SEN, SENP  
FB, COMP, MODE, BL  
AUX to COM  
RSP to RSN  
AUX  
67  
VBIAS  
16  
V
0
0
V
0
1
0
2
Sourcing current  
VBIAS  
0
2
mA  
COMP  
0
2
QG  
GATE loading  
20  
nC  
µF  
µF  
kΩ  
°C  
°C  
AUX load capacitance  
VBIAS load capacitance  
RFREQ  
0.8  
0.08  
30  
25  
1.5  
300  
125  
85  
TJ  
Operating junction temperature range  
Operating ambient temperature range  
-40  
-40  
TA  
(1) RSN, COM, and RTN should be tied together. SENP should be tied to VDD except for the buck configuration, where it should be tied to  
the output positive rail.  
(2) TMR, FREQ, CLASS, DET, VBIAS, and GATE should not be externally driven.  
(3) Junction temperature may be a constraining factor for high bias power designs.  
DISSIPATION RATINGS TABLE  
θJP  
θJC  
°C/W  
θJA  
θJA  
θJA  
MAXIMUM POWER RATING  
(W)(5)  
PACKAGE  
°C/W(1)  
°C/W(2)  
°C/W(3)  
°C/W(4)  
PWP (TSSOP-20)  
1.4  
26.62  
32.6  
151.9  
73.8  
1.2  
(1) Thermal resistance junction to pad.  
(2) See TI document SLMA002 for recommended layout. This is a best case, zero airflow number.  
(3) JEDEC method with low-k board (2 signal layers) and power pad not soldered (worst case).  
(4) JEDEC method with high-k board (4 layers, 2 signal and 2 planes) and power pad not soldered.  
(5) Based on TI recommended layout and 85°C ambient.  
3
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