TPS23750
TPS23770
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SLVS590A–JULY 2005–REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS
Characteristics are for: –40°C ≤ TJ ≤ 125°C; VDD – VSS = 48 V. VDD, CLASS, and DET referenced to VSS, and all
other pin voltages are referenced to RSN, COM, and RTN shorted together unless otherwise noted.
SEN=MODE=BL=RSP=RTN, FB=VBIAS, SENP=VDD, CTMR = 1000 pF, CVBIAS = 0.1 µF, CVAUX = 0.1 µF,
RFREQ = 150 kΩ, RDET = 24.9 kΩ, RCLASS = 255 Ω, GATE is unloaded, and VBIAS and AUX have no external loads
unless otherwise noted.
DC/DC CONTROLLER SECTION
RTN = VSS for this section only.
PARAMETER
BIAS SUPPLY (VBIAS)
VBIAS Output voltage
AUX SUPPLY (AUX)
VAUX Supply output voltage
Current limit
OSCILLATOR (FREQ)
TEST CONDITIONS
MIN
TYP MAX
UNIT
0 ≤ ILOAD ≤ 5 mA
4.60
5.1
5.5
V
18 V ≤ VVDD – COM ≤ 57 V, 0 mA ≤ IAUX ≤ 10 mA
9
10
11
28
V
VAUX = 0 V
12
23.5
mA
RFREQ = 30 kΩ, VCOMP = 3.9 V, MODE = VBIAS, Measure GATE
voltage at 50% rising to 50% falling
48.8
49.2
49.5
%
DMAX
Maximum duty cycle
MODE = VBIAS, VCOMP = 3 V, Measure at GATE
RFREQ = 30 kΩ
fOSC
Oscillator frequency
435
90
487
100
565
110
kHz
RFREQ = 150 kΩ
ERROR AMPLIFIER (FB, COMP)
COMP source current
0 ≤ VCOMP ≤ 4 V, FB = RTN, VTMR = 2.5 V
1.2 V ≤ VCOMP ≤ VBIAS, VTMR = 2.5 V
VCOMP = 2.5 V, VTMR = 2.5 V
2.5
2.4
1.47
80
mA
mA
V
COMP sink current
VREF
FB regulation voltage
1.50
1.53
Open loop voltage gain
1.2 V ≤ VCOMP ≤ 4 V, VTMR = 2.5 V
VCOMP = 2.5 V, VTMR = 2.5 V
dB
Small signal unity gain bandwidth
COMP input resistance
1.5
70
2
MHz
kΩ
µA
MODE = VBIAS, 1.1 ≤ VCOMP ≤ 4.4, VTMR = 2.5 V
0 ≤ VFB ≤ VBIAS, VTMR = 2.5 V
100
130
1
FB leakage (source or sink)
SOFT START TIMER (TMR)
Source current
TMR charging, VTMR between lower threshold and clamp
MODE = VBIAS, VCOMP = 4.4 V, Second cycle and beyond
38
9
50
10
62
11
10
µA
-
Ratio of source/sink current
ON duty cycle
8
9.1
%
CURRENT SENSE (RSP, RSN, BL)
MODE = VBIAS, VCOMP = 4.2 V, VTMR = 2.5 V, Increase
VRSP-RSN until the duty cycle switches from 50% to the minimum
0.46
0.70
0.5
0.54
0.83
V
V
Current limit threshold
Fault current threshold
MODE = VBIAS, VCOMP = 4.2 V, VTMR = 2.5 V, Increase
VRSP-RSN until no gate pulses occur
0.765
VRSP – RSN = 0.6 V, VAUX = 12 V, MODE = VBIAS, VCOMP = 4.2 V,
VTMR = 2.5 V. Measure 50% of VGATE↑ to 50% VGATE
↓
Minimum propagation delay, BL floating
40
45
60
70
90
95
tBLNK
Current limit delay
RSP current
ns
Blanking period (pulse width above minimum), BL connected to
RSN
Blanking period (pulse width above minimum), BL connected to
VBIAS
70
105
4
140
8
FREQ = VBIAS, MODE = VBIAS, VCOMP = 4 V,
VRSP-RSN = 0.4 V, IRSP sourcing
2.5
µA
GATE DRIVER (GATE)
Output voltage swing
5 mA source, VAUX = 12 V
11.9
V
5 mA sink, VAUX = 12 V
0.05
0.8
Peak source current
Peak sink current
VAUX = 12 V, pulse test
0.33
0.7
0.58
1.0
A
A
VAUX = 12 V, AC test or pulse test with TMR = RSN
1.3
VOLTAGE TRANSLATOR (SEN, SENP)
VTMR = 2.5 V, Measure with servo loop that includes the error
amplifier
(SENP - SEN) regulation voltage
1.456
1.492 1.526
V
4
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