TPS1HC100-Q1
ZHCSLK6A –JULY 2021 –REVISED DECEMBER 2021
www.ti.com.cn
6.5 Electrical Characteristics (continued)
VBB = 6 V to 28 V, TA = -40°C to 125°C (unless otherwise noted); Typical application is 13.5V, 10Ω, RILIM=Open (unless
otherwise specified)
PARAMETER
TEST CONDITIONS
No GND Network
MIN
TYP
MAX
UNIT
VIH, LATCH Input voltage high-level
1.5
V
VIHYS,
Input voltage hysteresis
280
mV
LATCH
RLATCH
Internal pulldown resistor
Input current low-level
Input current high-level
0.5
1
2.2
5
1.5
MΩ
µA
IIL, LATCH
IIH, LATCH
VDIA_EN = 0.8 V
VDIA_EN = 5 V
µA
6.6 SNS Timing Characteristics
VBB = 6 V to 18 V, TJ = -40°C to +150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SNS TIMING - CURRENT SENSE
VENx= 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, IL = 1A
Settling time from rising edge of DIA_EN
50% of VDIA_EN to 90% of settled ISNS
tSNSION1
tSNSION1
30
30
µs
µs
VEN = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, IL = 30 mA
Settling time from rising edge of DIA_EN
50% of VDIA_EN to 90% of settled ISNS
VEN = VDIA_EN = 0 V to 5 V
VBB = 13.5V RSNS = 1 kΩ, RLOAD
10Ω
Settling time from rising edge of EN and
DIA_EN
50% of VDIA_EN VEN to 90% of settled ISNS
tSNSION2
tSNSION3
tSNSIOFF
=
150
150
20
µs
µs
µs
VEN = 0 V to 5 V, VDIA_EN = 5 V VBB =
13.5V
RSNS = 1 kΩ, RLOAD = 10Ω
Settling time from rising edge of EN with
DIA_EN HI;
50% of VDIA_EN VEN to 90% of settled ISNS
VEN = 5 V, VDIA_EN = 5 V to 0 V VBB
= 13.5V
Settling time from falling edge of DIA_EN
RSNS = 1 kΩ, RL = 10 Ω
VEN = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 0.5 A to 3 A
tSETTLEH
tSETTLEL
Settling time from rising edge of load step
Settling time from falling edge of load step
20
20
µs
µs
VEN = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 3 A to 0.5 A
6.7 Switching Characteristics
VBB = 13.5 V, TJ = -40°C to +150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Channel Turnon delay time (from
Standby)
VBB = 13.5 V, RL = 10 Ω50% of EN
to 10% of VOUT
tDR
tDR
tDF
10
10
40
30
55
µs
Channel Turnon delay time (from
Active)
VBB = 13.5 V, RL = 10Ω50% of EN
to 10% of VOUT
45
45
µs
µs
VBB = 13.5 V, RL = 10 Ω50% of EN
to 90% of VOUT
Channel Turnoff delay time
VOUT rising slew rate
10
30
VBB = 13.5 V, 20% to 80% of VOUT
RL = 10 Ω
,
,
SRR
0.1
0.1
0.25
0.5
V/µs
VBB = 13.5 V, 80% to 20% of VOUT
SRF
fmax
tON
VOUT falling slew rate
Maximum PWM frequency(1)
Channel Turnon time
0.25
0.4
70
0.5
2
V/µs
kHz
µs
RL = 10 Ω
VBB = 13.5 V, RL = 10 Ω 50% of EN
to 80% of VOUT
30
39
145
VBB = 13.5 V, RL = 10Ω 50% of EN
to 20% of VOUT
tOFF
Channel Turnoff time
70
145
µs
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