SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
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In the 280x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
INT1
to
INT12
TINT0
PIE
CPU-TIMER 0
C28x
TINT1
INT13
XINT13
TINT2
INT14
CPU-TIMER 2
(Reserved for
DSP/BIOS)
CPU-TIMER 1
A.
B.
The timer registers are connected to the memory bus of the C28x processor.
The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4-2. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the
value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the
C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in
are used to configure the timers. For more information, see the
TMS320x280x,
2801x, 2804x DSP System Control and Interrupts Reference Guide
(literature number
Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
TIMER0TIM
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
Reserved
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
Reserved
TIMER1TPR
TIMER1TPRH
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
ADDRESS
0x0C00
0x0C01
0x0C02
0x0C03
0x0C04
0x0C05
0x0C06
0x0C07
0x0C08
0x0C09
0x0C0A
0x0C0B
0x0C0C
0x0C0D
0x0C0E
0x0C0F
0x0C10
0x0C11
0x0C12
0x0C13
0x0C14
SIZE (x16)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU-Timer 0, Counter Register
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
Reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
Reserved
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
CPU-Timer 2, Counter Register
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
DESCRIPTION
54
Peripherals
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