SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
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6.7
Clock Requirements and Characteristics
Table 6-8. Input Clock Frequency
PARAMETER
Resonator (X1/X2)
Crystal (X1/X2)
External oscillator/clock
source (XCLKIN or X1 pin)
100-MHz device
60-MHz device
MIN
20
20
4
4
1–5
TYP
MAX
35
35
100
60
MHz
MHz
UNIT
f
x
Input clock frequency
f
l
Limp mode SYSCLKOUT frequency range (with /2 enabled)
Table 6-9. XCLKIN
(1)
Timing Requirements - PLL Enabled
NO.
C8
C9
C10
C11
C12
(1)
t
c(CI)
t
f(CI)
t
r(CI)
t
w(CIL)
t
w(CIH)
Cycle time, XCLKIN
Fall time, XCLKIN
Rise time, XCLKIN
Pulse duration, XCLKIN low as a percentage of t
c(OSCCLK)
Pulse duration, XCLKIN high as a percentage of t
c(OSCCLK)
45
45
MIN
33.3
MAX
200
6
6
55
55
UNIT
ns
ns
ns
%
%
This applies to the X1 pin also.
Table 6-10. XCLKIN
(1)
Timing Requirements - PLL Disabled
NO.
C8
C9
C10
C11
C12
(1)
t
c(CI)
t
f(CI)
t
r(CI)
t
w(CIL)
t
w(CIH)
Cycle time, XCLKIN
Fall time, XCLKIN
Rise time, XCLKIN
Pulse duration, XCLKIN low as a percentage of t
c(OSCCLK)
Pulse duration, XCLKIN high as a percentage of t
c(OSCCLK)
100-MHz device
60-MHz device
Up to 20 MHz
20 MHz to 100 MHz
Up to 20 MHz
20 MHz to 100 MHz
45
45
MIN
10
16.67
MAX
250
250
6
2
6
2
55
55
ns
ns
ns
ns
%
%
UNIT
ns
This applies to the X1 pin also.
The possible configuration modes are shown in
Table 6-11. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
(1)
NO.
C1
C3
C4
C5
C6
t
c(XCO)
t
f(XCO)
t
r(XCO)
t
w(XCOL)
t
w(XCOH)
t
p
(1)
(2)
(3)
PARAMETER
Cycle time, XCLKOUT
Fall time, XCLKOUT
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
H–2
H–2
100-MHz device
60-MHz device
MIN
10
16.67
2
2
H+2
H+2
131072t
c(OSCCLK)
(3)
(2)
TYP
MAX
UNIT
ns
ns
ns
ns
ns
cycles
A load of 40 pF is assumed for these parameters.
H = 0.5t
c(XCO)
OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
106
Electrical Specifications
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