TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439I–JUNE 2007–REVISED MARCH 2011
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-16.
Table 3-16. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
ADDRESS
0x00 7011
SIZE (x16)
DESCRIPTION
PLLSTS
1
7
1
1
1
1
1
1
1
1
1
1
1
1
3
1
4
1
PLL Status Register
Reserved
Reserved
HISPCP
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
Reserved
PCLKCR3
PLLCR
0x00 7012 – 0x00 7018
0x00 701A
High-Speed Peripheral Clock Pre-Scaler Register
Low-Speed Peripheral Clock Pre-Scaler Register
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low Power Mode Control Register 0
Reserved
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 701F
0x00 7020
Peripheral Clock Control Register 3
PLL Control Register
0x00 7021
SCSR
0x00 7022
System Control and Status Register
Watchdog Counter Register
Reserved
WDCNTR
Reserved
WDKEY
Reserved
WDCR
0x00 7023
0x00 7024
0x00 7025
Watchdog Reset Key Register
Reserved
0x00 7026 – 0x00 7028
0x00 7029
Watchdog Control Register
Reserved
Reserved
MAPCNF
0x00 702A – 0x00 702D
0x00 702E
ePWM/HRPWM Re-map Register
3.6.1 OSC and PLL Block
Figure 3-9 shows the OSC and PLL block.
OSCCLK
OSCCLK
/1
XCLKIN
(3.3-V clock input
from external
oscillator)
0
n
OSCCLK or
VCOCLK
CLKIN
/2
/4
To
CPU
PLLSTS[OSCOFF]
PLLSTS[PLLOFF]
VCOCLK
PLL
n ≠ 0
PLLSTS[DIVSEL]
4-bit Multiplier PLLCR[DIV]
X1
External
Crystal or
Resonator
On-chip
oscillator
X2
Figure 3-9. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the 2833x/2823x devices using
the X1 and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of
the following configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low . The logic-high level in this case should not exceed VDDIO
.
2. A 1.9-V (1.8-V for 100 MHz devices) external oscillator can be directly connected to the X1 pin. The X2
pin should be left unconnected and the XCLKIN pin tied low . The logic-high level in this case should
not exceed .
Copyright © 2007–2011, Texas Instruments Incorporated
Functional Overview
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