TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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6.16 Multichannel Buffered Serial Port (McBSP) Timing
6.16.1 McBSP Transmit and Receive Timing
Table 6-55. McBSP Timing Requirements(1) (2)
NO.
MIN
MAX UNIT
McBSP module clock (CLKG, CLKX, CLKR) range
McBSP module cycle time (CLKG, CLKX, CLKR) range
1
kHz
(3)
25
MHz
ns
40
1
ms
ns
M11
M12
M13
M14
M15
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
tw(CKRX)
tr(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
P – 7
ns
7
7
ns
tf(CKRX)
Fall time, CLKR/X
ns
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
18
2
ns
M16
M17
M18
M19
M20
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
0
ns
ns
ns
ns
ns
6
18
2
0
6
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
18
2
0
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
CLKSRG
(1 ) CLKGDV)
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG =
CLKSRG can be LSPCLK, CLKX,
CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (25 MHz).
174
Electrical Specifications
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