TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439I–JUNE 2007–REVISED MARCH 2011
6.16.2 McBSP as SPI Master or Slave Timing
Table 6-57. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M30 tsu(DRV-CKXL)
M31 th(CKXL-DRV)
M32 tsu(BFXL-CKXH)
M33 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P(1)
(1) 2P = 1/CLKG
Table 6-58. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN
2P(1)
P
MAX
MAX
M24
M25
M28
th(CKXL-FXL)
td(FXL-CKXH)
tdis(FXH-DXHZ)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
ns
ns
ns
Disable time, DX high impedance following
last data bit from FSX high
6
6P + 6
4P + 6
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
ns
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by
setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will
be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
M33
M32
MSB
LSB
CLKX
FSX
M25
M24
M28
M29
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M30
M31
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 6-37. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Copyright © 2007–2011, Texas Instruments Incorporated
Electrical Specifications
177
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