TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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Table 6-2. TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
(1)
(2)
(3)
(4)
IDD
IDDIO
TYP(5)
IDD3VFL
TYP
IDDA18
TYP(5)
IDDA33
TYP(5)
MODE
TEST CONDITIONS
TYP(5)
MAX
MAX
MAX
MAX
MAX
The following peripheral
clocks are enabled:
•
•
•
•
•
ePWM1/2/3/4/5/6
eCAP1/2/3/4/5/6
eQEP1/2
eCAN-A
SCI-A/B
(FIFO mode)
Operational
(Flash)(6)
290 mA
315 mA
30 mA
50 mA
35 mA
40 mA
30 mA
35 mA
1.5 mA
2 mA
•
•
•
•
SPI-A (FIFO mode)
ADC
I2C
CPU Timer 0/1/2
All PWM pins are toggled
at 150 kHz.
All I/O pins are left
(7)
unconnected.
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
IDLE
100 mA
120 mA
15 mA
60 μA
120 mA
2 μA
10 μA
5 μA
60 μA
15 μA
20 μA
•
•
•
•
eCAN-A
SCI-A
SPI-A
I2C
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT(8)
8 mA
60 μA
60 μA
120 μA
120 μA
2 μA
2 μA
10 μA
10 μA
5 μA
5 μA
60 μA
60 μA
15 μA
15 μA
20 μA
20 μA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(9)
150 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Table 6-67. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
(3) IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(4) IDDA33 includes current into VDDA2 and VDDAIO pins.
(5) The TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125°C, and MAX voltage (VDD
2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
=
(6) When the identical code is run off SARAM, IDD would increase as the code operates with zero wait states.
(7) The following is done in a loop:
•
•
•
•
•
•
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Multiplication/addition operations are performed.
Watchdog is reset.
ADC is performing continuous conversion. Data from ADC is transferred to SARAM through the DMA.
32-bit read/write of the XINTF is performed.
GPIO19 is toggled.
(8) HALT mode IDD currents will increase with temperature in a non-linear fashion.
(9) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
120
Electrical Specifications
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