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TMS320F28335ZJZS 参数 Datasheet PDF下载

TMS320F28335ZJZS图片预览
型号: TMS320F28335ZJZS
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置PC时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SPRS439I – JUNE 2007 – REVISED MARCH 2011
www.ti.com
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8
Clocking and Nomenclature (100-MHz Devices)
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Input Clock Frequency
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XCLKIN Timing Requirements – PLL Disabled
............................................................................
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
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Power Management and Supervisory Circuit Solutions
...................................................................
Reset (XRS) Timing Requirements
..........................................................................................
General-Purpose Output Switching Characteristics
........................................................................
General-Purpose Input Timing Requirements
..............................................................................
IDLE Mode Timing Requirements
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IDLE Mode Switching Characteristics
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STANDBY Mode Timing Requirements
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STANDBY Mode Switching Characteristics
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HALT Mode Timing Requirements
...........................................................................................
HALT Mode Switching Characteristics
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ePWM Timing Requirements
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ePWM Switching Characteristics
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Trip-Zone Input Timing Requirements
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High-Resolution PWM Characteristics at SYSCLKOUT = (60 –150 MHz)
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Enhanced Capture (eCAP) Timing Requirement
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eCAP Switching Characteristics
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Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
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eQEP Switching Characteristics
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External ADC Start-of-Conversion Switching Characteristics
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External Interrupt Timing Requirements
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External Interrupt Switching Characteristics
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I2C Timing
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SPI Master Mode External Timing (Clock Phase = 0)
....................................................................
SPI Master Mode External Timing (Clock Phase = 1)
....................................................................
SPI Slave Mode External Timing (Clock Phase = 0)
......................................................................
SPI Slave Mode External Timing (Clock Phase = 1)
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Relationship Between Parameters Configured in XTIMING and Duration of Pulse
...................................
XINTF Clock Configurations
..................................................................................................
External Interface Read Timing Requirements
.............................................................................
External Interface Read Switching Characteristics
.........................................................................
External Interface Write Switching Characteristics
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External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
...................................
External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
.......................................
Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
.......................................
Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
.......................................
External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
...................................
Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
.......................................
Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
......................................
XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
......................................................
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
.................................................
ADC Electrical Characteristics (over recommended operating conditions)
............................................
ADC Power-Up Delays
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Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
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XCLKIN Timing Requirements – PLL Enabled
List of Tables
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