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SPRS439I – JUNE 2007 – REVISED MARCH 2011
shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK x 4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
(Current CPU
Frequency)
OSCCLK/2
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, t
p
) is
131072 OSCCLK Cycles Long.)
OSCCLK * 4
(Changed CPU Frequency)
Figure 6-8. Example of Effect of Writing Into PLLCR Register
6.9
6.9.1
General-Purpose Input/Output (GPIO)
GPIO - Output Timing
Table 6-12. General-Purpose Output Switching Characteristics
PARAMETER
MIN
All GPIOs
All GPIOs
MAX
8
8
25
UNIT
ns
ns
MHz
t
r(GPO)
t
f(GPO)
t
fGPO
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
GPIO
t
r(GPO)
t
f(GPO)
Figure 6-9. General-Purpose Output Timing
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Electrical Specifications
131
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