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TMS320F28335ZJZS 参数 Datasheet PDF下载

TMS320F28335ZJZS图片预览
型号: TMS320F28335ZJZS
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置PC时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
SPRS439IJUNE 2007REVISED MARCH 2011  
www.ti.com  
Table 6-59. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)  
MASTER  
SLAVE  
NO.  
UNIT  
MIN  
30  
1
MAX  
MIN MAX  
M39 tsu(DRV-CKXH)  
M40 th(CKXH-DRV)  
M41 tsu(FXL-CKXH)  
M42 tc(CKX)  
Setup time, DR valid before CLKX high  
Hold time, DR valid after CLKX high  
Setup time, FSX low before CLKX high  
Cycle time, CLKX  
8P – 10  
ns  
ns  
ns  
ns  
8P – 10  
16P + 10  
16P  
2P(1)  
(1) 2P = 1/CLKG  
Table 6-60. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)  
MASTER  
MIN  
SLAVE  
MIN  
NO.  
PARAMETER  
UNIT  
MAX  
MAX  
M34  
M35  
M37  
th(CKXL-FXL)  
td(FXL-CKXH)  
tdis(CKXL-DXHZ)  
Hold time, FSX low after CLKX low  
Delay time, FSX low to CLKX high  
P
2P(1)  
ns  
ns  
ns  
Disable time, DX high impedance following last data bit  
from CLKX low  
P + 6  
7P + 6  
4P + 6  
M38  
td(FXL-DXV)  
Delay time, FSX low to DX valid  
6
ns  
(1) 2P = 1/CLKG  
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2  
by setting CLKSM = CLKGDV = 1. With a maximum LSPCLK speed of 75 MHz, CLKX maximum  
frequency is LSPCLK/16; that is, 4.6875 MHz and P = 13.3 ns.  
M42  
MSB  
LSB  
M41  
CLKX  
FSX  
DX  
M35  
M34  
M37  
M38  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-2)  
(n-3)  
(n-4)  
M39  
M40  
(n-2)  
DR  
Bit 0  
(n-3)  
(n-4)  
Figure 6-38. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0  
178  
Electrical Specifications  
Copyright © 2007–2011, Texas Instruments Incorporated  
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232