TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439I–JUNE 2007–REVISED MARCH 2011
V , V
DDIO DD3VFL
V , V
DDA2 DDAIO
(3.3 V)
V , V
DD DD1A18,
V
DD2A18
(1.9 V/1.8 V)
XCLKIN
X1/X2
(A)
OSCCLK/8
OSCCLK/16
XCLKOUT
User-Code Dependent
t
OSCST
t
w(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
(Internal)
User-Code Execution Phase
User-Code Dependent
t
d(EX)
(B)
h(boot-mode)
t
Boot-Mode
Pins
GPIO Pins as Input
Boot-ROM Execution Starts
Peripheral/GPIO Function
Based on Boot Code
(C)
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
I/O Pins
A. Upon power up, SYSCLKOUT is OSCCLK/4. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register
come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains
why XCLKOUT = OSCCLK/16 during this phase. Subsequently, boot ROM changes SYSCLKOUT to OSCCLK/2.
Because the XTIMCLK register is unchanged by the boot ROM, XCLKOUT is OSCCLK/8 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
C. See Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up.
Figure 6-6. Power-on Reset
Copyright © 2007–2011, Texas Instruments Incorporated
Electrical Specifications
129
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TMS320F28232
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