TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O – MARCH 1999 – REVISED JANUARY 2005
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5.5.11
5.5.11.1
Host-Port Interface Timing
HPI8 Mode
processor clock (see Figure 5-28 through Figure 5-31). In the following tables, DS refers to the logical OR
of HCS, HDS1, and HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands
for HCNTL0, HCNTL1, and HR/W.
Table 5-32. HPI8 Mode Timing Requirements
5416-120
5416-160
MIN
t
su(DSL-HBV)
t
h(DSL-HBV)
t
su(HSL-DSL)
t
w(DSL)
t
w(DSH)
t
su(HDV-DSH)
t
h(DSH-HDV)W
t
su(GPIO-COH)
t
h(GPIO-COH)
Setup time, HBIL and HAD valid before DS low (when HAS is not used), or HBIL and HAD
valid before HAS low
Hold time, HBIL and HAD valid after DS low (when HAS is not used), or HBIL and HAD
valid after HAS low
Setup time, HAS low before DS low
Pulse duration, DS low
Pulse duration, DS high
Setup time, HD valid before DS high, HPI write
Hold time, HD valid after DS high, HPI write
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose
input
Hold time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
6
3
8
13
7
3
2
3
0
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
86
Electrical Specifications
TI [ TEXAS INSTRUMENTS ]
