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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O – MARCH 1999 – REVISED JANUARY 2005
Table 5-26. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
(1)
5416-120
5416-160
MASTER
MIN MAX
t
su(BDRV-BCKXL)
t
h(BCKXH-BDRV)
(1)
(2)
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX high
12
4
SLAVE
MIN MAX
2 – 6P
(2)
5 + 12P
(2)
ns
ns
UNIT
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock.
Table 5-27. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
(1)
5416-120
5416-160
PARAMETER
MASTER
(2)
MIN
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
d(BCKXL-BDXV)
t
dis(BCKXL-BDXHZ)
t
d(BFXL-BDXV)
(1)
(2)
(3)
Hold time, BFSX low after BCLKX low
(3)
Delay time, BFSX low to BCLKX high
(4)
Delay time, BCLKX low to BDX valid
Disable time, BDX high impedance following last data bit from
BCLKX low
Delay time, BFSX low to BDX valid
C –3
T–4
–4
–2
D–
2
MAX
C+4
T+3
5
4
D+4
6P + 2
(5)
6P – 4
(5)
4P + 2
(5)
10P + 17
(5)
10P + 17
(5)
8P + 17
(5)
SLAVE
MIN
MAX
ns
ns
ns
ns
ns
UNIT
(4)
(5)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) *2P when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and (CLKGDV/2 + 1) * 2P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FRSRM = 2 for master McBSP
CLKXM = CLKRm = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the
master clock (BCLKX).
P = 0.5 * processor clock.
LSB
BCLKX
t
h(BCKXL-BFXL)
BFSX
t
dis(BCKXL-BDXHZ)
BDX
Bit 0
t
su(BDRV-BCKXL)
BDR
Bit 0
Bit(n-1)
t
d(BFXL-BDXV)
Bit(n-1)
t
d(BCKXL-BDXV)
(n-2)
t
h(BCKXH-BDRV)
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
t
d(BFXL-BCKXH)
MSB
Figure 5-25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
Electrical Specifications
83
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