T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
HPI8 timing (continued)
†‡§
timing requirements
(see Figure 35, Figure 36, Figure 37, and Figure 38)
MIN
5
MAX
UNIT
ns
¶#
Setup time, HBIL and HAD valid before DS low or before HAS low
t
t
su(HBV-DSL)
¶#
Hold time, HBIL and HAD valid after DS low or after HAS low
5
ns
h(DSL-HBV)
t
t
t
t
t
t
t
Setup time, HAS low before DS low
Pulse duration, DS low
10
20
10
2
ns
ns
ns
ns
ns
ns
ns
su(HSL-DSL)
w(DSL)
Pulse duration, DS high
w(DSH)
Setup time, HDx valid before DS high, HPI write
Hold time, HDx valid after DS high, HPI write
su(HDV-DSH)
h(DSH-HDV)W
su(GPIO-COH)
h(GPIO-COH)
3
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
Hold time, HDx input valid after CLKOUT high, HDx configured as general-purpose input
6
0
†
DS refers to the logical OR of HCS, HDS1, and HDS2.
‡
§
¶
#
HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
HAD refers to HCNTL0, HCNTL1, and H/RW.
When the HAS signal is used to latch the control signals, this timing refers to the falling edge of the HAS signal. Otherwise, when HAS is not used
(always high), this timing refers to the falling edge of DS.
62
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