T MS 3 20 VC 54 02
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
HPI8 timing
†‡§¶
switching characteristics over recommended operating conditions
(see Figure 35, Figure 36, Figure 37, and Figure 38)
[H = 0.5t
]
c(CO)
PARAMETER
MIN
2
MAX
UNIT
t
Enable time, HD driven from DS low
16
ns
en(DSL-HD)
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
18H+16 – t
w(DSH)
t
< 18H
w(DSH)
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
16
26H+16 – t
16
t
≥ 18H
w(DSH)
Case 1c: Memory access when
DMAC is active in 32-bit mode and
w(DSH)
t
< 26H
Delay time, DS low to HDx valid for
first byte of an HPI read
w(DSH)
t
ns
d(DSL-HDV1)
Case 1d: Memory access when
DMAC is active in 32-bit mode and
t
≥ 26H
w(DSH)
Case 2a: Memory accesses when
DMAC is inactive and t < 10H
10H+16 – t
16
w(DSH)
w(DSH)
Case 2b: Memory accesses when
DMAC is inactive and t ≥ 10H
w(DSH)
Case 3: Register accesses
16
16
5
t
t
t
t
Delay time, DS low to HDx valid for second byte of an HPI read
Hold time, HDx valid after DS high, for a HPI read
Valid time, HDx valid after HRDY high
ns
ns
d(DSL-HDV2)
h(DSH-HDV)R
v(HYH-HDV)
d(DSH-HYL)
3
9
Delay time, DS high to HRDY low (see Note 1)
16
ns
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode
18H+16
Case 1b: Memory accesses when
DMAC is active in 32-bit mode
26H+16
10H+16
6H+16
ns
ns
t
Delay time, DS high to HRDY high
d(DSH-HYH)
Case 2: Memory accesses when
DMAC is inactive
Case 3: Write accesses to HPIC
register (see Note 2)
16
3
ns
ns
ns
t
t
t
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
d(HCS-HRDY)
)
d(COH-HYH
5
d(COH-HTX)
d(COH-GPIO)
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output.
t
6
ns
NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.
2. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronoulsy, and do not cause HRDY to be deasserted.
DS refers to the logical OR of HCS, HDS1, and HDS2.
HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
†
‡
§
¶
GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI [ TEXAS INSTRUMENTS ]
