T MS 3 20 VC 54 02
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
†
timing requirements for McBSP as SPI master or slave: [H=0.5t
(see Figure 31)
] CLKSTP = 10b, CLKXP = 0
c(CO)
MASTER
SLAVE
MIN MAX
UNIT
MIN
9
MAX
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
– 12H
ns
ns
su(BDRV-BCKXL)
0
5 + 12H
h(BCKXL-BDRV)
t
t
Setup time, BFSX low before BCLKX high
Cycle time, BCLKX
10
ns
ns
su(BFXL-BCKXH)
12H
32H
c(BCKX)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
CLKXP = 0† (see Figure 31)
] CLKSTP = 10b,
c(CO)
‡
MASTER
SLAVE
UNIT
PARAMETER
MIN MAX
MIN
MAX
§
t
t
t
Hold time, BFSX low after BCLKX low
T – 3 T + 4
C – 5 C + 3
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXH-BDXV)
¶
Delay time, BFSX low to BCLKX high
Delay time, BCLKX high to BDX valid
–2
6
6H + 5 10H + 15
Disable time, BDX high impedance following last data bit from
BCLKX low
t
C – 2 C + 3
ns
dis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
t
t
2H+ 4
4H – 2
6H + 17
8H + 17
ns
ns
dis(BFXH-BDXHZ)
Delay time, BFSX low to BDX valid
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
t
MSB
c(BCKX)
LSB
t
su(BFXL-BCKXH)
BCLKX
BFSX
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
dis(BFXH-BDXHZ)
t
d(BFXL-BDXV)
t
t
d(BCKXH-BDXV)
(n-2)
dis(BCKXL-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-3)
(n-4)
t
su(BDRV-BCLXL)
t
h(BCKXL-BDRV)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 31. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
57
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