T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing
†
timing requirements for McBSP [H=0.5t
] (see Figure 28 and Figure 29)
c(CO)
MIN
MAX
UNIT
ns
t
t
Cycle time, BCLKR/X
BCLKR/X ext
4H
c(BCKRX)
Pulse duration, BCLKR/X high or BCLKR/X low
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKR/X ext
BCLKR/X ext
2H–2
ns
w(BCKRX)
8
1
0
3
5
0
0
4
7
0
0
3
t
t
t
t
t
t
Setup time, external BFSR high before BCLKR low
ns
ns
ns
ns
ns
ns
su(BFRH-BCKRL)
h(BCKRL-BFRH)
su(BDRV-BCKRL)
h(BCKRL-BDRV)
su(BFXH-BCKXL)
h(BCKXL-BFXH)
Hold time, external BFSR high after BCLKR low
Setup time, BDR valid before BCLKR low
Hold time, BDR valid after BCLKR low
Setup time, external BFSX high before BCLKX low
Hold time, external BFSX high after BCLKX low
t
t
Rise time, BCKR/X
Fall time, BCKR/X
8
8
ns
ns
r(BCKRX)
f(BCKRX)
†
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
†
switching characteristics for McBSP [H=0.5t
] (see Figure 28 and Figure 29)
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
t
t
Cycle time, BCLKR/X
BCLKR/X int
BCLKR/X int
4H
c(BCKRX)
‡
‡
‡
Pulse duration, BCLKR/X high
D – 2
C – 2
D + 2
ns
w(BCKRXH)
‡
t
Pulse duration, BCLKR/X low
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
C + 2
ns
ns
ns
w(BCKRXL)
–2
3
2
9
4
t
Delay time, BCLKR high to internal BFSR valid
Delay time, BCLKX high to internal BFSX valid
d(BCKRH-BFRV)
0
t
ns
ns
ns
d(BCKXH-BFXV)
8
11
4
–1
3
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
t
dis(BCKXH-BDXHZ)
9
¶
0
7
§
t
Delay time, BCLKX high to BDX valid
Delay time, BFSX high to BDX valid
DXENA = 0
d(BCKXH-BDXV)
d(BFXH-BDXV)
3
¶
11
BFSX int
BFSX ext
–1
3
t
ns
3
13
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
T = BCLKRX period = (1 + CLKGDV) * 2H
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
The transmit delay enable (DXENA) and A–bis mode (ABIS) features of the McBSP are not implemented on the TMS320VC5402.
Minimum delay times also represent minimum output hold times.
§
¶
54
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