T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
reset, BIO, interrupt, and MP/MC timings
timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 t
and Figure 24)
] (see Figure 22, Figure 23,
c(CO)
MIN
0
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, RS after CLKOUT low
Hold time, BIO after CLKOUT low
Hold time, INTn, NMI, after CLKOUT low
Hold time, MP/MC after CLKOUT low
h(RS)
0
h(BIO)
†
0
h(INT)
0
h(MPMC)
w(RSL)
‡§
Pulse duration, RS low
4H+5
2H+2
4H
2H
4H
2H+2
4H
10
5
Pulse duration, BIO low, synchronous
Pulse duration, BIO low, asynchronous
w(BIO)S
w(BIO)A
w(INTH)S
w(INTH)A
w(INTL)S
w(INTL)A
w(INTL)WKP
su(RS)
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
¶
Setup time, RS before X2/CLKIN low
Setup time, BIO before CLKOUT low
7
10
10
su(BIO)
Setup time, INTn, NMI, RS before CLKOUT low
Setup time, MP/MC before CLKOUT low
7
su(INT)
5
su(MPMC)
†
The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure
synchronization and lock-in of the PLL.
‡
§
¶
Note that RS may cause a change in clock frequency, therefore changing the value of H.
Divide-by-two mode
50
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