T MS 3 20 VC 54 02
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
HOLD and HOLDA timings
timing requirements for memory control signals and HOLDA, [H = 0.5 t
] (see Figure 21)
c(CO)
MIN
4H+7
7
MAX
UNIT
ns
t
t
Pulse duration, HOLD low
w(HOLD)
Setup time, HOLD low/high before CLKOUT low
ns
su(HOLD)
switching characteristics over recommended operating conditions for memory control signals
and HOLDA, [H = 0.5 t
] (see Figure 21)
c(CO)
PARAMETER
MIN
MAX
5
UNIT
ns
t
t
t
t
t
t
Disable time, address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, address, PS, DS, IS from CLKOUT low
dis(CLKL-A)
dis(CLKL-RW)
dis(CLKL-S)
en(CLKL-A)
en(CLKL-RW)
en(CLKL-S)
5
ns
5
ns
2H+5
2H+5
2H+5
ns
Enable time, R/W enabled from CLKOUT low
ns
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
2
–1
ns
2
2
ns
ns
ns
Valid time, HOLDA low after CLKOUT low
t
t
v(HOLDA)
–1
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
2H–1
w(HOLDA)
CLKOUT
t
su(HOLD)
t
su(HOLD)
t
w(HOLD)
HOLD
t
v(HOLDA)
t
t
v(HOLDA)
t
w(HOLDA)
HOLDA
dis(CLKL-A)
t
en(CLKL-A)
A[19:0]
PS, DS, IS
D[15:0]
R/W
t
t
t
t
dis(CLKL-RW)
dis(CLKL-S)
dis(CLKL-S)
en(CLKL-RW)
t
en(CLKL-S)
MSTRB
IOSTRB
t
en(CLKL-S)
Figure 21. HOLD and HOLDA Timings (HM = 1)
49
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