ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢈꢈꢊ
ꢋ ꢌꢍ ꢎꢏꢐꢑꢒ ꢌ ꢓꢀ ꢏꢌ ꢔꢌ ꢀꢕꢖ ꢂꢌ ꢔ ꢓꢕꢖ ꢑꢗ ꢒ ꢆꢎ ꢂ ꢂꢒ ꢗ ꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 39)
−150
−167
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
26
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 − 6P
ns
ns
su(DRV-CKXL)
6 + 12P
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
†‡
slave: CLKSTP = 10b, CLKXP = 0 (see Figure 39)
−150
−167
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
T − 9 T + 9
L − 9 L + 9
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
−9
9
6P + 4 10P + 20
Disable time, DX high impedance following last data bit from
CLKX low
6
t
L − 9 L + 9
ns
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
2P + 3
4P + 2
6P + 20
8P + 20
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TI [ TEXAS INSTRUMENTS ]
