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SPRS073L − AUGUST 1998 − REVISED JUNE 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
switching characteristics over recommended operating conditions for McBSP (see Figure 37)
−150
−167
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from
CLKS input
1
t
4
26
ns
d(CKSH-CKRXH)
§¶
2
3
4
t
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
2P
ns
ns
ns
c(CKRX)
#
#
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
C − 1
C + 1
w(CKRX)
−11
−11
3
3
3
9
4
9
d(CKRH-FRV)
9
t
t
t
Delay time, CLKX high to internal FSX valid
ns
ns
ns
d(CKXH-FXV)
dis(CKXH-DXHZ)
d(CKXH-DXV)
−9
3
Disable time, DX high impedance following last data bit
from CLKX high
12
13
||
||
−9+ D1
3 + D1
4 + D2
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
||
||
19 + D2
FSX int
FSX ext
−1
3
3
9
14
t
ns
d(FXH-DXV)
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
†
‡
§
¶
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
The minimum CLKR/X period is twice the CPU cycle time (2P). This means that the maximum bit rate for communications between the McBSP
and other device is 83 Mbps for 167 MHz CPU clock or 75 Mbps for 150 MHz CPU clock; where the McBSP is either the master or the slave.
Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP
communications is 33 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 30 ns (33 MHz), whichever
value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 30 ns as the minimum CLKR/X clock cycle (by setting the appropriate
CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock
cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with
CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY =
01b or 10b) and the other device the McBSP communicates to is a slave.
#
C = H or L
S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
If DXENA = 0, then D1 = D2 = 0
||
If DXENA = 1, then D1 = 2P, D2 = 4P
70
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