Functional Overview
3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor
reads one character from the receiver FIFO.
4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received
or after the microprocessor reads the receiver FIFO.
When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as
follows:
1. The transmitter holding register empty interrupt [IIR (3−0) = 2] occurs when the transmit FIFO is empty.
It is cleared [IIR (3−0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit
FIFO while servicing this interrupt) or the IIR is read.
2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time
when there have not been at least two bytes in the transmitter FIFO at the same time since the last time
that the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.
3.13.4 FIFO Polled Mode Operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts
the UART in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately,
either one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:
•
•
LSR0 is set as long as there is one byte in the receiver FIFO.
LSR1 − LSR4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode; the IIR is not affected since IER2 = 0.
•
•
•
LSR5 indicates when the THR is empty.
LSR6 indicates that both the THR and TSR are empty.
LSR7 indicates whether there are any errors in the receiver FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver
and transmitter FIFOs are still fully capable of holding characters.
3.13.5 Interrupt Enable Register (IER)
The IER enables each of the five types of interrupts (refer to Table 3−17) and enables INTRPT in response to
an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents
of this register are summarized in Table 3−15 and are described in the following bullets.
•
•
•
•
Bit 0: When set, this bit enables the received data available interrupt.
Bit 1: When set, this bit enables the THRE interrupt.
Bit 2: When set, this bit enables the receiver line status interrupt.
Bits 3 through 7: These bits are not used
3.13.6 Interrupt Identification Register (IIR)
The UART has an on-chip interrupt generation and prioritization capability that permits flexible communication
with the CPU.
The UART provides three prioritized levels of interrupts:
•
•
•
Priority 1 − Receiver line status (highest priority)
Priority 2 − Receiver data ready or receiver character time-out
Priority 3 − Transmitter holding register empty
54
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
