Functional Overview
NOTE: The clock rates in Table 3−20 and Table 3−21 are shown, for example only, to illustrate
the relationship of clock rate and divisor value, to baud rate and baud rate error. Typically,
higher clock rates will normally be used, and error values will differ accordingly.
Table 3−20. Baud Rates Using a 1.8432-MHz Clock
DIVISOR USED
TO GENERATE
16 × CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
DESIRED
BAUD RATE
50
75
2304
1536
1047
857
768
384
192
96
110
0.026
0.058
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
64
58
0.69
48
32
24
16
12
6
3
2
2.86
Table 3−21. Baud Rates Using a 3.072-MHz Clock
DIVISOR USED
TO GENERATE
16 × CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
DESIRED
BAUD RATE
50
75
3840
2560
1745
1428
1280
640
320
160
107
96
110
0.026
0.034
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
0.312
80
53
0.628
1.23
40
27
20
10
5
58
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
