Functional Overview
S
e
l
e
c
t
Receiver
FIFO
8
Receiver
Shift
Register
RX
Data
Bus
Buffer
Receiver
Buffer
Register
Peripheral
Bus
8
Receiver
Timing and
Control
Line
Control
Register
Divisor
Latch (LS)
Baud
Generator
Divisor
Latch (MS)
Transmitter
Timing and
Control
Line
Status
Register
Transmitter
FIFO
S
e
l
e
c
t
Transmitter
Shift
Register
Transmitter
Holding
Register
8
8
TX
Modem
Control
Register
Control
Logic
Interrupt
Enable
Register
Interrupt
Control
Logic
8
Interrupt
Identification
Register
8
INTRPT
(To CPU)
FIFO
Control
Register
Figure 3−22. UART Functional Block Diagram
50
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
