Functional Overview
Data Space (0000
−
005F)
Hex
0000
Reserved
001F
0020
DRR20
0021
DRR10
DXR20
0022
0023
DXR10
0024
Reserved
002F
DRR22
0030
DRR12
0031
DXR22
0032
0033
DXR12
0034
Data Space
0000
Data Space
(See Breakout)
005F
0060
007F
0080
1FFF
2000
3FFF
4000
Reserved
5FFF
6000
003F
0040
0041
0042
0043
0044
7FFF
8000
9FFF
A000
Scratch-Pad
RAM
On-Chip
DARAM0
8K Words
On-Chip
DARAM1
8K Words
On-Chip
DARAM2
†
8K Words
On-Chip
DARAM3
†
8K Words
On-Chip
DARAM4
†
8K Words
I/O Space
Hex
0000
Reserved
DRR21
DRR11
DXR21
DXR11
Reserved
005F
Reserved
†
FFFF
Reserved on the 5404
FFFF
Figure 3−20. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
3.12.4
DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple DMA
channels that are assigned to the same priority level are handled in a round-robin manner.
3.12.5
DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
3.12.6
DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers
can be preloaded for the next block transfer through the DMA reload registers (DMGSA, DMGDA, DMGCR,
and DMGFR). Autoinitialization allows:
•
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfers, but with the reload registers, it can reinitialize these values for
the next block transfer any time after the current block transfer begins.
Repetitive operation: The CPU does not preload the reload register with new values for each block transfer
but only loads them on the first block transfer.
•
46
SPRS007D
November 2001
−
Revised April 2004
TI [ TEXAS INSTRUMENTS ]
