Functional Overview
3.6.2 Programmable Bank-Switching
Programmable bank-switching logic allows the 5407/5404 to switch between external memory banks without
requiring external wait states for memories that need additional time to turn off. The bank-switching logic
automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or
data space.
Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at
address 0029h. The bit fields of the BSCR are shown in Figure 3−9 and are described in Table 3−5.
15
CONSEC
R/W-1
14
DIVFCT
R/W-11
13
12
IACKOFF
R/W-1
3
Reserved
R
LEGEND:
R = Read, W = Write,
n = value after reset
2
HBH
R/W-0
11
Reserved
R
1
BH
0
Reserved
R
Figure 3−9. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
Table 3−5. Bank-Switching Control Register (BSCR) Fields
BIT
NAME
RESET
VALUE
CONSEC = 0:
15
CONSEC
†
1
CONSEC = 1:
FUNCTION
Consecutive bank-switching. Specifies the bank-switching mode.
Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for
continuous memory reads (i.e., no starting and trailing cycles between read cycles).
Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:
starting cycle, read cycle, and trailing cycle.
CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency
equal to 1/(DIVFCT+1) of the DSP clock.
13−14
13 14
DIVFCT
11
DIVFCT = 00:
DIVFCT = 01:
DIVFCT = 10:
DIVFCT = 11:
12
11−3
IACKOFF
Reserved
1
−
IACKOFF = 0:
IACKOFF = 1:
Reserved
HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset
.
2
HBH
0
HBH = 0:
HBH = 1:
The bus holder is disabled except when HPI16=1.
The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous
logic level.
The bus holder is disabled.
The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic
level.
CLKOUT is not divided.
CLKOUT is divided by 2 from the DSP clock.
CLKOUT is divided by 3 from the DSP clock.
CLKOUT is divided by 4 from the DSP clock (default value following reset).
The IACK signal output off function is disabled.
The IACK signal output off function is enabled.
IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.
Bus holder. Controls the bus holder. BH is cleared to 0 at reset.
1
BH
0
BH = 0:
BH = 1:
Reserved
0
†
Reserved
−
For additional information, see Section 3.11 of this document.
32
SPRS007D
November 2001
−
Revised April 2004
TI [ TEXAS INSTRUMENTS ]
