Introduction
2.2.2 Pin Assignments for the PGE Package
The TMS320VC5407/TMS320VC5404PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are
shown in Figure 2−2.
1
108
107
106
105
104
103
102
101
100
99
V
A22
A18
A17
SS
2
3
V
SS
V
SS
4
DV
DD
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
5
A10
HD7
A11
A12
A13
A14
A15
6
7
8
9
10
11
12
13
14
15
16
98
CV
DD
97
HAS
96
V
V
95
HD3
CLKOUT
SS
SS
DD
94
CV
93
V
SS
HCS 17
HR/W 18
READY 19
PS 20
92
HPIENA
CV
91
DD
90
V
SS
89
TMS
DS 21
88
TCK
IS 22
87
TRST
R/W 23
86
TDI
MSTRB 24
IOSTRB 25
MSC 26
XF 27
HOLDA 28
IAQ 29
HOLD 30
BIO 31
MP/MC 32
85
TDO
84
EMU1/OFF
EMU0
TOUT
HD2
HPI16
CLKMD3
CLKMD2
CLKMD1
83
82
81
80
79
78
77
DV
DD
33
V
SS
76
V
SS
34
DV
DD
75
BDR2 35
BFSRX2
BDX2
BCLKRX2
74
36
73
NOTE A: DV is the power supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for both the I/O pins and
DD
DD
SS
the core CPU.
Figure 2−2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)
17
November 2001 − Revised April 2004
SPRS007D
TI [ TEXAS INSTRUMENTS ]
