Features
1
TMS320VC5407/TMS320VC5404 Features
D
D
D
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D
D
D
Instructions With a 32-Bit Long Word
Operand
Instructions With Two- or Three-Operand
Reads
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
Arithmetic Instructions With Parallel Store
and Parallel Load
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
D
D
D
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
− On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With
External Clock Source
− Two 16-Bit Timers
− Six-Channel Direct Memory Access
(DMA) Controller
− Three Multichannel Buffered Serial Ports
(McBSPs)
− 8/16-Bit Enhanced Parallel Host-Port
Interface (HPI8/16)
− Universal Asynchronous Receiver/
Transmitter (UART) With Integrated Baud
Rate Generator
D
D
D
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D
D
Data Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
D
D
On-Chip ROM
− 128K × 16-Bit (5407) Configured for
D
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
Program Memory
− 64K × 16-Bit (5404) Configured for
Program Memory
D
D
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
On-Chip RAM
− 40K x 16-Bit (5407) Composed of
Five Blocks of 8K × 16-Bit On-Chip
Dual-Access Program/Data RAM
− 16K x 16-Bit (5404) Composed of
Two Blocks of 8K × 16-Bit On-Chip
Dual-Access Program/Data RAM
†
IEEE Std 1149.1 (JTAG) Boundary Scan
Logic
D
D
D
144-Pin Ball Grid Array (BGA)
(GGU Suffix)
144-Pin Low-Profile Quad Flatpack (LQFP)
(PGE Suffix)
D
D
Enhanced External Parallel Interface (XIO2)
Single-Instruction-Repeat and
8.33-ns Single-Cycle Fixed-Point
Block-Repeat Operations for Program Code
Instruction Execution Time (120 MIPS)
D
Block-Memory-Move Instructions for Better
Program and Data Management
D
D
3.3-V I/O Supply Voltage
1.5-V Core Supply Voltage
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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13
November 2001 − Revised April 2004
SPRS007D
TI [ TEXAS INSTRUMENTS ]
