Introduction
Table 2−2. Signal Descriptions (Continued)
TERMINAL
NAME
†
I/O
DESCRIPTION
OSCILLATOR/TIMER PINS
CLKOUT
O/Z
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine
cycle is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when
OFF is low.
CLKMD1
CLKMD2
CLKMD3
I
I
Clock mode external/internal input signals. CLKMD1−CLKMD3 allows you to select and configure different
clock modes such as crystal, external clock, various PLL factors.
X2/CLKIN
Input pin to internal oscillator from the crystal. If the internal oscillator is not being used, an external clock
source can be applied to this pin. The internal machine cycle time is determined by the clock operating
mode pins (CLKMD1, CLKMD2 and CLKMD3).
X1
O
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision depended,
see Section 3.10 for additional information.)
TOUT
O
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT
cycle wide. TOUT also goes into the high-impedance state when OFF is low.
TOUT1
I/O/Z
Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is a
CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI, and TOUT1 is only
available when the HPI is disabled.
MULTICHANNEL BUFFERED SERIAL PORT PINS
BCLKR0
BCLKR1
BCLKRX2
I/O/Z
I
Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver. BCLKRX2
is McBSP2 transmit AND receive clock.
BDR0
BDR1
BDR2
Serial data receive input.
BFSR0
BFSR1
BFSRX2
I/O/Z
I/O/Z
O/Z
I/O/Z
Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over
BDR. BFSRX2 is McBSP2 transmit AND receive frame sync.
BCLKX0
BCLKX1
Transmit clock. BCLKX serves as the serial shift clock for the buffered serial port transmitter. The BCLKX
pins are configured as inputs after reset. BCLKX goes into the high-impedance state when OFF is low.
BDX0
BDX1
BDX2
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted or when OFF is low.
BFSX0
BFSX1
Frame synchronization pulse for transmit output. The BFSX pulse initiates the transmit data process over
BDX. The BFSX pins are configured as inputs after reset. BFSX goes into the high-impedance state when
OFF is low.
UART
TX
RX
O
I
UART asynchronous serial transmit data output.
UART asynchronous serial receive data input.
†
I = Input, O = Output, Z = High-impedance, S = Supply
20
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
