TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990
instruction set
The TMS320C2x microprocessor implements a comprehensive instruction set that supports both
numeric-intensive signal processing operations as well as general-purpose applications, such as
multiprocessing and high-speed control. The TMS32020 source code is upward-compatible with TMS320C25
source code. TMS32020 object code runs directly on the TMS320C25.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the
same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary
depending upon whether the next data operand fetch is from internal or external memory. Highest throughput
is achieved by maintaining data memory on-chip and using either internal or fast external program memory.
addressing modes
The TMS320C2x instruction set provides three memory addressing modes: direct, indirect, and immediate
addressing.
Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the
instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data
memory address. Indirect addressing accesses data memory through the auxiliary registers. In immediate
addressing, the data is based on a portion of the instruction word(s).
In direct memory addressing, the instruction word contains the lower seven bits of the data memory address.
This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus,
memory is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words.
Up to eight auxiliary registers (AR0-AR7) provide flexible and powerful indirect addressing (five on the
TMS32020, eight on the TMS320C25). To select a specific auxiliary register, the Auxiliary Register Pointer
(ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
Thereareseventypesofindirectaddressing:auto-incrementorauto-decrement, post-indexingbyeitheradding
or subtracting the contents of AR0, single indirect addressing with no increment or decrement, and bit-reversal
addressing (used in FFTs on the TMS320C25 only) with increment or decrement. All operations are performed
on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary
register and ARP may be modified.
repeat feature
A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table
read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC) is loaded
with either a data memory value (RPT instruction) or an immediate value (RPTK instruction). The value of this
operand is one less than the number of times that the next instruction is executed. Those instructions that are
normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle
instructions.
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