TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990
scaling shifter
The TMS320C2x scaling shifter has 16-bit input connected to the data bus and a 32-bit output connected to the
ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction.
The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign-extended,
depending upon the status programmed into the SXM (sign-extension mode) bit of status register ST1.
16
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16-bit parallel multiplier
The 16
×
16-bit hardware multiplier is capable of computing a signed or unsigned 32-bit product in a single
machine cycle. The multiplier has the following two associated registers.
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A 16-bit Temporary Register (TR) that holds one of the operands for the multiplier, and
A 32-bit Product Register (PR) that holds the product.
Incorporated into the instruction set are single-cycle multiply/accumulate instructions that allow both operands
to be processed simultaneously. The data for these operations may reside anywhere in internal or external
memory, and can be transferred to the multiplier each cycle via the program and data buses.
Four product shift modes are available at the Product Register (PR) output that are useful when performing
multiply/accumulate operations, fractional arithmetic, or justifying fractional products.
timer
The TMS320C2x provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM)
register is a down counter that is continuously clocked by CLKOUT1 on the TMS320C25. The timer is clocked
by CLKOUT1/4 on the TMS32020. A timer interrupt (TINT) is generated every time the timer decrements to zero.
The timer is reloaded with the value contained in the period (PRD) register within the next cycle after it reaches
zero so that interrupts may be programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT 1 on the
TMS320C25 or 4
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PRD
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CLKOUT 1 cycles on the TMS32020.
memory control
The TMS320C2x provides a total of 544 16-bit words of on-chip data RAM, divided into three separate blocks
(B0, B1, and B2). Of the 544 words, 288 words (blocks B1 and B2) are always data memory, and 256 words
(block B0) are programmable as either data or program memory. A data memory size of 544 words allows the
TMS320C2x to handle a data array of 512 words (256 words if on-chip RAM is used for program memory), while
still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can
be downloaded from external program memory into on-chip RAM and then executed.
When using on-chip program RAM, ROM, EPROM, or high-speed external program memory, the TMS320C2x
runs at full speed without wait states. However, the READY line can be used to interface the TMS320C2x to
slower, less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program
RAM speeds processing while cutting system costs.
The TMS320C2x provides three separate address spaces for program memory, data memory, and I/O. The
on-chip memory is mapped into either the 64K-word data memory or program memory space, depending upon
the memory configuration (see Figure 1). The CNFD (configure block B0 as data memory) and CNFP (configure
block B0 as program memory) instructions allow dynamic configuration of the memory maps through software.
Regardless of the configuration, the user may still execute from external program memory.
The TMS320C2x has six registers that are mapped into the data memory space: a serial port data receive
register, serial port data transmit register, timer register, period register, interrupt mask register, and global
memory allocation register.
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