Functional Overview
3.11 Enhanced External Parallel Interface (XIO2)
The 5407/5404 external interface has been redesigned to include several improvements, including:
simplification of the bus sequence, more immunity to bus contention when transitioning between read and
write operations, the ability for external memory access to the DMA controller, and optimization of the
power-down modes.
The bus sequence on the 5407/5404 still maintains all of the same interface signals as on previous 54x
devices, but the signal sequence has been simplified. Most external accesses now require 3 cycles composed
of a leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide
additional immunity against bus contention when switching between read operations and write operations. To
maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous
54x devices is available.
Figure 3–15 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode,
or single memory reads in consecutive mode. The accesses shown in Figure 3–15 always require 3 CLKOUT
cycles to complete.
CLKOUT
A[22:0]
D[15:0]
READ
R/W
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Read
Cycle
Trailing
Cycle
Figure 3–15. Nonconsecutive Memory Read and I/O Read Bus Sequence
28
SPRS007B
November 2001 – Revised July 2003
TI [ TEXAS INSTRUMENTS ]
