Functional Overview
The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using
time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save
memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for
transmission and reception. All 128 channels in a bit stream consisting of a maximum of 128 channels can
be enabled.
15
Reserved
R
10
9
XMCME
R/W
8
XPBBLK
R/W
7
XPBBLK
R/W
6
XPABLK
R/W
5
4
XCBLK
R
2
1
XMCM
R/W
0
LEGEND:
R = Read, W = Write
Figure 3–12. Multichannel Control Register (MCR1)
15
Reserved
R
10
9
RMCME
R/W
8
RPBBLK
R/W
7
RPBBLK
R/W
6
RPABLK
R/W
5
4
RCBLK
R
2
1
Reserved
R
0
RMCM
R/W
LEGEND:
R = Read, W = Write
Figure 3–13. Multichannel Control Register (MCR2)
The 5407/5404 McBSP has two working modes:
•
•
In the first mode, when (R/X)MCME = 0, it is comparable with the McBSPs used in the 5410 where the
normal 32-channel selection is enabled (default).
In the second mode, when (R/X)MCME = 1, it has 128-channel selection capability. Multichannel control
register Bit 9, (R/X)MCME, is used as the 128-channel selection enable bit. Once (R/X)MCME = 1, twelve
new registers ((R/X)CERC – (R/X)CERH) are used to enable the 128-channel selection.
The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface protocol.
Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by
the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured
to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave.
Although the BCLKS pin is not available on the 5407/5404 PGE and GGU packages, the 5407/5404 is capable
of synchronization to external clock sources. BCLKX or BCLKR can be used by the sample rate generator for
external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the PCR to
accommodate this option.
November 2001 – Revised July 2003
SPRS007B
25
TI [ TEXAS INSTRUMENTS ]
