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SPRS439M –JUNE 2007–REVISED AUGUST 2012
CPU bus
INT7
ADC
CPU
PF0
I/F
External
interrupts
CPU
timers
ADC
control
and
ADC
RESULT
PIE
ADC
PF2
I/F
ADC
DMA
PF0
I/F
registers RESULT
registers
L4
SARAM
(4Kx16)
L4
I/F
CPU
L5
SARAM
(4Kx16)
McBSP A
L5
I/F
Event
triggers
DMA
6-ch
McBSP B
ePWM/
HRPWM(A)
registers
PF3
I/F
L6
SARAM
(4Kx16)
L6
I/F
L7
SARAM
(4Kx16)
L7
I/F
DMA bus
A. The ePWM and HRPWM registers must be remapped to PF3 (through bit 0 of the MAPCNF register) before they can
be accessed by the DMA. The ePWM or HRPWM connection to DMA is not present in silicon revision 0.
Figure 4-1. DMA Functional Block Diagram
Copyright © 2007–2012, Texas Instruments Incorporated
Peripherals
65
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